1. Field of the Invention
The present invention relates to a charge detection device used, for example, in combination with a charge transfer device such as a charge coupled device (hereinafter, referred to as a "CCD"), a method for producing the same, and a charge transfer and detection apparatus including such a charge detection device and a charge transfer device.
2. Description of the Related Art
Charge transfer devices such as CCDs are widely used for, for example, image sensors. Especially, buried-channel type CCDs, in which a signal charge is transferred in the state of being kept far from a surface of a semiconductor layer and thus without being influenced by the surface, have a high transfer efficiency. For such an advantage, most of the CCDs in practical use are of the buried-channel type. For converting a signal charge transferred by the CCDs into a voltage signal, various detection devices have been proposed.
Briefly referring to FIGS. 13A and 13B, a charge detection device of a floating diffusion amplifier (hereinafter, referred to as "FDA") type will be described. FIG. 13A is a schematic top view of a charge detection device 81 of the FDA type, and FIG. 13B is a diagram illustrating the potential distribution in the direction in which a signal charge is transferred in the charge detection device 81.
As is shown in FIG. 13A, the charge detection device 81 is provided at an end area of a charge transfer device 100 for receiving a transfer clock .phi..sub.1. The charge detection device 81 includes an output gate section 101 for receiving an input gate signal OG, a floating diffusion (hereinafter, referred to as "FD") section 102, a reset gate section 103 for receiving a reset gate signal .phi..sub.R, and a reset drain section 104 for receiving a reset drain signal RD in this order in the signal charge transfer direction. The FD section 102 is connected to the gate of a driving transistor T.sub.D of a source follower 10.
The charge detection device 81 operates in the following manner.
When a signal charge Q.sub.sig reaches the FD section 102 via the output gate section 101, the signal charge Q.sub.sig is converted into a voltage V.sub.sig expressed by Equation (1) by a capacitance C.sub.FD generated by the FD section 102, a wire connected to the FD section 102, the gate of the driving transistor T.sub.D, and the like. EQU V.sub.sig =Q.sub.sig /C.sub.FD (1)
The voltage V.sub.sig is amplified, namely, reduced in impedance by the source follower 10, and then is output to an external device. The signal charge in the FD section 102 is sent to the reset drain section 104 via the reset gain section 103 every transfer period. In other words, the potential of the FD section 102 is reset to a reset voltage every transfer period.
The charge detection device 81 of the FDA type has the following problems.
As is shown in FIG. 13B, the potential of the FD section 102 becomes higher or lower than a potential B of the reset drain section 104 by a slight level .DELTA.V.sub.a during the reset operation by the channel thermal noise of the resets gate section 103 or the like, thereby Generating reset noise. Further, the capacitance C.sub.FD, which includes various elements including the junction capacitance of the FD section 102, the capacitance of the wire connected to the FD section 102, and the gate capacitance of the driving transistor T.sub.D, is limited in reduction. For these reasons, the gain of conversion of a signal charge into a voltage signal cannot be sufficiently high.
In order to solve such a problem, a charge detection device of a floating Gate amplifier (hereinafter, referred to as "FGA") type shown in FIGS. 14A and 14B has been proposed. FIG. 14A is a schematic top view of a charge detection device 82 of an FGA type, and FIG. 14B is a diagram illustrating the potential distribution in the signal charge transfer direction in the charge detection device 82.
As is shown in FIG. 14A, the charge detection device 82 includes a floating Gate 110 in a middle area of the charge transfer device 100. The floating gate 110 is connected to the Gate of the driving transistor T.sub.D of the source follower 10.
As is shown in FIG. 14B, when the signal charge Q.sub.sig is transferred to below the floating gate 110, the potential of the floating gate 110 is modulated by the signal charge Q.sub.sig and output to an external device via the source follower 10. The floating gate 110 is capacitively coupled with a bias electrode V.sub.B.
Since the charge detection device 82 of the FGA type includes no reset gate section, and thus channel thermal noise is not generated, generation of reset noise is prevented. Nonetheless, this type of charge detection device 82 has a problem in that, since the potential of the floating gate 110 is controlled only in terms of the capacitance, drift or the like cannot be prevented, and thus stability is not sufficient.
Further, in the case of the charge detection device 82 of the FGA type, as in the charge detection device 81 of the FDA type, a section for converting a signal charge into a voltage signal and a section for amplifying the voltage signal are configured separately. For this reason, the capacitance includes the capacitance of the floating gate 110, the capacitance of the wire connected to the floating gate 110, and the capacitance of the gate of the driving transistor T.sub.D, and thus cannot be reduced sufficiently. Accordingly, enhancement of the gain of conversion of a signal charge into a voltage signal is limited.
Under these circumstances, charge detection devices including a section for converting a signal charge into a voltage signal and a current amplification circuit formed on the same plane in an integrated manner have recently been proposed.
As a first example of such a charge detection device, a floating surface detector (hereinafter, referred to as an "FSD") described in R. J. Brewer, A Low Noise CCD Output Amplifier, IEDM Tech. Dig., pp. 610-612 (December, 1978) will be described with reference to FIGS. 15A through 15D. FIG. 15A is a schematic top view of such an FSD 83, FIG. 15B is a diagram illustrating the potential distribution in the signal charge transfer direction, FIG. 15C is a cross sectional view of the FSD 83 taken along line E--E in FIG. 15A, and FIG. 15D is a diagram illustrating the potential distribution in the depth direction of the FSD 83 along line F--F in FIG. 15C.
As is shown in FIGS. 15A and 15C, the FSD 83 includes a gate section 120 for receiving a DC potential instead of the floating gate, and a buried channel below the gate section 120 is continued from the channel in the charge transfer device. A p.sup.+ -type source region 121 and a p.sup.+ -type drain region 122 are provided to sandwich the channel in the direction perpendicular to the signal charge transfer direction.
By appropriately setting the level of a voltage V.sub.G of the gate section 120, a surface channel is formed in a surface region of an n-type semiconductor layer 125 below the gate section 120. The surface region is immediately below a surface of the semiconductor layer 125. The surface channel has an opposite polarity to that of the n-type semiconductor layer 125. The surface channel, the source region 121 and the drain region 122 are included in a P-MOS (metal-oxide-semiconductor) transistor. When a signal charge is accumulated in the buried channel in the n-type semiconductor layer 125 below the gate section 120, the potential of the surface channel changes. Such a potential is detected and output. In detail, as is shown in FIG. 15A, the drain region 122 of the P-MOS transistor is connected to a negative power source having a voltage of, for example, -15 V, and the source region 121 of the P-MOS transistor is connected to a positive power source having a voltage of, for example, +15 V via a resistor 123, and then a potential V.sub.S of the source region 121 is output via a buffer amplifier 124.
In the FSD 83 having the above-described structure, the buried channel acts as a conversion section for converting a signal charge into a voltage signal, and the P-MOS transistor including the surface channel and the source and the drain regions 121 and 122 acts as an amplifier. The conversion section and the amplifier are provided in an integrated manner.
As a second example of a charge detection device including a conversion section and an amplifier in an integrated manner, a charge detection device of a floating surface amplifier (hereinafter, referred to as "FSA") type described in Matsunaga, High Sensitivity Charge Detectors for Charge Coupled Devices, ITEJ Technical Report Vol. 13, No. 64, pp. 21-24, IPU '89-30 (December 1989) will be described with reference to FIGS. 16A and 16B. FIG. 16A is a cross sectional view of a charge detection device 84 of the FSA type, and FIG. 16B is a diagram illustrating the potential distribution in the depth direction of the charge detection device 84.
As is illustrated in FIG. 16A, the charge detection device 84 of the FSA type includes an n-type semiconductor layer 130 including a source region 133 and a drain region 134. A gate section 131 similar to the gate section 120 in terms of structure is provided sufficiently far from the n-type semiconductor layer 130, and a floating gate 132 is provided above and close to the n-type semiconductor layer 130. In such a structure, the capacitance of a signal accumulation section is significantly reduced, thereby enhancing the sensitivity of the charge detection device 84. A surface channel immediately below a surface of the semiconductor layer 130 of a detection section, the source and the drain regions 133 and 134 are included in a P-MOS transistor.
In the charge detection device 84, the semiconductor layer 130 below the floating gate 132 acts as a conversion section for converting a signal charge into a voltage signal, and the P-MOS transistor acts as an amplifier.
As a third example of a charge detection device including a conversion section and an amplifier in an integrated manner, a charge detection device of a floating well amplifier (hereinafter, referred to as "FWA") type also described in Matsunaga, High Sensitivity Charge Detectors for Charge Coupling Devices, ITEJ Technical Report Vol. 13, No. 64, pp. 21-24, IPU '89-30 (December 1989) will be described with reference to FIGS. 17A and 17B. FIG. 17A is a cross sectional view of a charge detection device 85 of the FWA type, and FIG. 17B is a diagram illustrating the potential distribution in the depth direction of the charge detection device 85.
As is illustrated in FIG. 17A, the charge detection device 85 of the FWA type includes an n-type semiconductor layer 140 including a source region 143 and a drain region 144. A gate section 141 similar to the gate section 120 in terms of structure is provided sufficiently far from the n-type semiconductor layer 140, and a floating gate 142 is provided above and close to the n-type semiconductor layer 140. In such a structure, the capacitance of a signal accumulation section is significantly reduced, thereby enhancing the sensitivity of the charge detection device 85. A channel in a p-well 145 below the n-type semiconductor layer 140, the source and the drain regions 143 and 144 are included in a P-MOS transistor.
In the charge detection device 85, the semiconductor layer 140 below the floating gate 142 acts as a conversion section for converting a signal charge into a voltage signal, and the P-MOS transistor acts as an amplifier.
As a fourth example of a charge detection device including a conversion section and an amplifier in an integrated manner, a charge detection device of a ring junction gate (hereinafter, referred to as "RJG") type described in Morimoto et al., Low Noise Ring-Junction-Gate Amplifier for CCD Signal Charge Detection, Lecture Notes on the ITEJ National Convention, pp. 27-28, (1989) will be described with reference to FIG. 18. FIG. 18 is a cross sectional view of a charge detection device 86 of the RJG type.
As is illustrated in FIG. 18, the charge detection device 86 of the RJG type includes no gate region or floating gate. A p.sup.+ -type source region 151 is provided in a middle part of a detection section.
In the charge detection device 86 having such a structure, an n-type layer 152 provided in a surface region of the detection section acts as a conversion section for converting a signal charge into a voltage signal, and a section including a p-well 153, the source region 151, and a p.sup.+ -type drain region 154 acts as an amplifier.
The charge detection devices of the FSD, FSA, FWA, and RJG types have the following problems in linearity and noise.
Linearity PA0 Noise
First, problems from the view point of one dimensional function, namely, the function in the depth direction will be described.
Returning to FIG. 15D, the problems of the charge detection device 83 of the FSD type will be described.
Where the thickness of a spatial charge layer of a signal accumulation section S on the side of the surface of the charge detection device 83 is d.sub.1, and the thickness of the spatial charge layer on the side of a substrate of the charge detection device 83 is d.sub.2 (the thickness of the gate insulating film is calculated as a thickness of a film formed of a semiconductor material), a level of change .DELTA.V.sub.S of a surface potential V.sub.S caused by the quantity of change .DELTA.Q.sub.S of the signal charge Q.sub.sig is expressed by Equation (2). The surface potential V.sub.S is detected by the P-MOS transistor acting as the detection section. In Equation (2), C.sub.O is the capacitance of the gate insulating film per unit area, and A.sub.S is the area of the signal accumulation section S. EQU .DELTA.V.sub.S =d.sub.2 /(d.sub.1 +d.sub.2).multidot.(.DELTA.Q.sub.S /(C.sub.O A.sub.S)) (2)
Since C.sub.O and A.sub.S are considered to be constant, if d.sub.1 &lt;&lt;d.sub.2, .DELTA.V.sub.S is substantially in proportion to .DELTA.Q.sub.S.
In the case of the charge detection device 84 of the FSA type, as is shown in FIG. 16B, a level of change .DELTA.V.sub.S of the surface potential V.sub.S caused by the quantity of change .DELTA.Q.sub.S of the signal charge Q.sub.sig is expressed by Equation (2). If d.sub.1 &lt;&lt;d.sub.2, .DELTA.V.sub.S is substantially in proportion to .DELTA.Q.sub.S.
In the case of the charge detection device 85 of the FWA type, as is shown in FIG. 17B, where the thickness of an area of the spatial charge layer on the side of the substrate, the area between the most shallow point of the potential and the substrate is d.sub.3, a level of change .DELTA.V.sub.S of a potential V.sub.S of the p-well 145 caused by the quantity of change .DELTA.Q.sub.S of the signal charge Q.sub.sig is expressed by Equation (3). In Equation (3), K.sub.1 and K.sub.2 are each a factor of proportionality. EQU V.sub.S =K.sub.1 .multidot.(d.sub.3).sup.2 .DELTA.d.sub.3 =K.sub.2 .multidot.d.sub.1 /(d.sub.1 +d.sub.2).multidot.(.DELTA.Q.sub.S /A.sub.S) (3)
The designation .DELTA.d.sub.3, which is the level of change of d.sub.3, is substantially in proportion to the quantity of change .DELTA.Q.sub.S of the signal charge Q.sub.sig , but the level of change .DELTA.V.sub.S is not in proportion to .DELTA.Q.sub.S.
The charge detection device 86 of the RJG type can be considered to include a gate electrode farther from the n-type layer 152 than in the charge detection device 85 of the FWA type. Accordingly, if d.sub.1 &gt;&gt;d.sub.2 in Equation (3), the level of change .DELTA.V.sub.S is not in proportion to the quantity of change .DELTA.Q.sub.S.
As is apparent from the above description, the charge detection devices of the FWA type and the RJG type are not satisfactory in linearity even if only from the view point of the depth direction.
Linearity from the view point of the two- or three-dimensional function, namely, in the planar directions will be described hereinafter.
Referring to, for example, FIG. 15B, the potential is deep in the detection section and becomes shallower in the surrounding area in a step-like manner. In actuality, however, as is represented by a solid line in FIG. 19B in relation with a cross sectional view of a conventional charge detection device (FIG. 19A), the potential in the surrounding area gradually changes due to the fringe field effect. Such effect of gradually changing the potential is referred to as the two-dimensional effect. The two-dimensional effect also acts in the direction perpendicular to the signal charge transfer direction. Thus, the potential distribution is represented by a cone-shaped potential well. For this reason, the area of the signal accumulation section is not constant, but increases as the charge increases. The dashed line in FIG. 19B represents an ideal box-shaped potential well.
The fringe field effect causing the two-dimensional effect is more conspicuous in the buried channel type charge detection devices in which the signal charge is accumulated far from the surface of the semiconductor layer than in the surface channel type charge detection devices in which the signal charge is accumulated in the surface region of the semiconductor layer. The reason is that the coupling of the capacitances of the signal charge and the gate electrode are weaker in the buried channel type devices than in the surface channel type devices.
The charge detection devices of the FSD, FSA, FWA and RJG types are all of the buried channel type, and the signal charge is accumulated in an area where a charge is transferred. The linearity in such conventional charge detection devices including a conversion section and an amplifier in an integrated manner is reduced by the two-dimensional effect.
In the charge detection devices including a conversion section and an amplifier in an integrated manner, the buried channel is completely depleted when a signal charge is transferred from the detection section by a reset operation. Accordingly, no reset noise is generated.
In the charge detection devices of the FWA and RJG types, the channel of the P-MOS transistor is a p-well, namely, buried. Accordingly, the P-MOS transistor as an amplifier is not influenced by the interface level, and thus generates low noise. In the charge detection devices of the FSD and FSA types, the channel of the P-MOS transistor is in the surface region of the semiconductor layer, and thus is influenced by the interface level, thereby generating high noise.
As has been described so far, the charge detection devices of the FSD and FSA types have satisfactory one-dimensional linearity but generate high noise. The charge detection devices of the FWA and RJG types generate low noise but have low one-dimensional linearity. The charge detection devices of all the four types have low two-dimensional linearity.